NXP Semiconductors /MIMXRT1062 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B1_11

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_AD_B1_11

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: FLEXSPIA_DATA02 of instance: flexspi

1 (ALT1): Select mux mode: ALT1 mux port: EWM_OUT_B of instance: ewm

2 (ALT2): Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8

3 (ALT3): Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1

4 (ALT4): Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2

7 (ALT7): Select mux mode: ALT7 mux port: KPP_COL02 of instance: kpp

8 (ALT8): Select mux mode: ALT8 mux port: ENET2_1588_EVENT1_IN of instance: enet2

9 (ALT9): Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO11 of instance: flexio3

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B1_11

Links

() ()